The power supplies of the next generation of central processing units (CPUs) will require switching-mode DC—DC converters that operate at very high frequencies and supply high levels of current. For example, such a DC—DC converter might be required to operate at a frequency of 1-4 MHz and supply a current of 50-60 A for laptop CPUs and 90-100 A for desktop CPUs. The structure and operation of switching-mode DC—DC converters is well known and several examples are described, for example, in U.S. Pat. No. 6,031,702, incorporated herein by reference in its entirety.
An analysis of the total power loss of both the upper and lower power switches in a step-down DC—DC buck converter is described in Wen Wei et al., “Desktop Voltage Regulator, Power/Thermal Solutions”, Intel Technology Symposium, Aug. 28-29, 2002.
The amount of power dissipated in a field-effect transistor (FET) switch in a high-frequency DC—DC converter is dominated by (i) switching (on/off) losses and (ii) gate drive losses. These losses are governed by the following formulas:
Switching losses:       P    switch    =            1      2        ⁢          V              i        ⁢                                   ⁢        n              ⁢          I      out        ⁢          t      on        ⁢    f  where Vin is the input (supply) voltage, I is the output current, f is the switching frequency, and ton is the switching time of the device. i.e., the time it takes the device to switch from “on” to “off”. Of these parameters only ton is determined by the characteristics of the device. The other parameters are controlled by the application.
Gate drive losses:       P    gate    =            1      2        ⁢    C    ⁢                   ⁢          V      gs      2        ⁢    f  where Pgate is the power loss in the gate drive of the switch, C is the input capacitance of the switch, Vgs is the voltage that charges the capacitance (i.e., the voltage required to switch the power device on and off), and f is the operating frequency.
As the formula indicates, the “gate drive power loss” of the switch is directly proportional to the input capacitance and operating frequency and to the square of the voltage. Therefore, to reduce the power loss when the operating frequency is increased, it is necessary to reduce the voltage and the input capacitance. It is particularly important to reduce the voltage, since a reduction of the voltage by a factor of 4, for example, reduces the power loss by a factor of 16. Voltage-scaling is therefore a key element in the design of very high-frequency DC—DC converters.
As indicated in the above-referenced U.S. Pat. No. 6,031,702, MOSFETs are typically used to perform the power switching function in DC—DC converters. A typical MOSFET might require a gate drive of 4 to 5 V to switch it on and off. This voltage level leads to unduly high power losses, however.
Another possibility would be to perform the switching function with a junction field-effect transistor (JFET), shown in cross-section in FIGS. 1A and 1B. JFET 10 includes an N+ source region 102, and N+ drain region 104 and P+ gate 106, which are formed as opposing regions separated by an N− channel region 108. While P+ gate 106 is shown as two separate regions, it is understood that they are electrically connected in the third dimension outside the plane of the paper. The width of channel region 108 is designated XW. The input capacitance Cin of JFET 10 is equal to:Cin=Cgs+Cgd where Cgs equals the capacitance between P+ gate 106 and N+ source region 102 and Cgd equals the capacitance between P+ gate and N+ drain region 104.
If N+ source region 102 abuts P+ gate 106, as shown in FIG. 1A, Cgs is high, and as a result the input capacitance of the device is very high. As indicated above, this is not acceptable.
On the other hand, if N+ source region 102 is separated from P+ gate by a distance XS, as shown in FIG. 1B, Cgs is reduced, but the channel width XW is increased by an amount equal to 2XS. This reduces the packing density of the device, reducing the total channel width per unit area and increasing the on-resistance Rdson. Moreover, the pinch-off voltage VGp is proportional to the square of the channel width XW.VGp∝XW2 
Therefore, increasing the channel width XW by 2XS increases the pinch-off voltage and this in turn leads to greater switching losses.
Furthermore, when the P+ gate 106 is forward-biased with respect to the N-channel region 108, holes are injected from P+ gate 106 into N-channel region 108. This additional stored charge increases Cin by roughly an order of magnitude and slows down the switching speed and increases the power dissipated in the device. Also, when the load is inductive, Cgd becomes very high. For these reasons, a JFET is generally considered to be a less desirable device than a MOSFET for performing the power switching function in high-frequency DC—DC converters.
Accordingly, it would be desirable to develop a switching device that has a low input capacitance and that can be switched on and off by at a significantly lower voltage than is possible with conventional MOSFETs and JFETs.